While you can read about the chip's 1.86 to 2.13 GHz frequency, their 42 - 52 Dollar price, their 32nm manufacturing, their NM10 chipset and similar basics elsewhere, I am going to concentrate on some peculiar facts that either just surfaced or were confirmed through Intels data sheet for Intel's D2000 and N2000 series of Atom processors: The missing DirectX 10.1 support, (almost) no power management for the IGP or the limited video decoding support.
Atom D2x00 & N2x00 SKUs
Of course, as is customary for Atom processors, Intel relies on Hyper Threading Technology in order to squeeze out the maximum performance from their in-order-architecture. Also, the slower of the desktop parts – D2500 – will not be available with HTT activated, making it a 2C/2T processor. All of the described Cedar Trails processors have Intels 64-bit extension to the x86 ISA available as well as supporting SSE2, 3 and SSSE3. They get serviced with a single channel of DDR3 memory with 800 or 1066 MT/s where the Desktop parts and the higher end N2800 can access up to two SODIMMs, and the N2600 being limited to only one. That makes for a total of 4 GiByte of DDR3 memory on D2700, D2500 and N2800 and half of that (2 GiB) for N2600 SKUs.
For those of you looking at Cedar Trail as interesting low-power multimedia devices, there are a few caveats. First, High Definition Copy Protection (HDCP) is implemented only in D2700 and N2800 and not in the slower two SKUs. While this could possibly amended by the device or board manufacturer, there's more. According to Intel, the integrated graphics core of both D2x00 and N2x00 support the following
•full MPEG2 (VLD/ iDCT/MC)
•WMV
• Fast video Composing
• HW decode/ acceleration for MPEG4 Part 10 (AVC/H.264) & VC-1; 720p60, 1080i60, 1080p@24 up to 20 Mps
• D2700 and N2800 processor supports Blu-Ray* 2.0 playback - 1 x HD and 1 x SD
streaming
• Video image Enhancement: Hue, Saturation, Brightness, Contrast (HSBC) adjust,
Bob De-Interlacing
• Support two Streams of 1080p HD @ 267 MHz
•WMV
• Fast video Composing
• HW decode/ acceleration for MPEG4 Part 10 (AVC/H.264) & VC-1; 720p60, 1080i60, 1080p@24 up to 20 Mps
• D2700 and N2800 processor supports Blu-Ray* 2.0 playback - 1 x HD and 1 x SD
streaming
• Video image Enhancement: Hue, Saturation, Brightness, Contrast (HSBC) adjust,
Bob De-Interlacing
• Support two Streams of 1080p HD @ 267 MHz
• Blu-Ray 2.0 playback for D2500 and N2600 processor
• MPEG4 part2 does not utilize Next Generation Intel Atom Processor based
desktop platform H/W
• No hardware assist for Flash Decode from Adobe 11.0 and onwards
• MPEG4 part2 does not utilize Next Generation Intel Atom Processor based
desktop platform H/W
• No hardware assist for Flash Decode from Adobe 11.0 and onwards
While the D2x00 models will only have C0 (full-on) and C1 (AutoHALT start), there's complete C0 to C6 support availbable for the mobile parts N2x00. This also means, there will be no Speed-Stepping for the Desktop-SKUs. Deep Power Down mode C6 can be entered by each thread individually with the last thread to go to sleep has also the ability to shrink the still powered-on amount of L2 cache. The display parts will have only D0 (Full-on) and D3 (off) for all parts though, so power saving in the graphics core seems not to have a high priority for Intel here. If that's because PowerVR's SGX545 is a mobile design in it's heart and thus power consumption without this feature is already low enough is just one of the possibilties, with cost being another.
The thermal design power (note: not the peak power!) for the Desktop parts will thus amount to <= 10 watts according to Intel - interestingly, this also applies to a yet unannounced D2000-part with 2.4 Ghz and assumes a maximum temperature inside the processor of 100° C. Not surprisingly the idle power consumption is much lower (in part due to being specified to only 50 degress centigrade) and is stated to be ~2.72 and ~2.74 watts respectively. In contrast, the average power consumption of the mobile SKUs N2600 and N2800 is only ~1.09 and ~1.81 watts with all the power saving bells and whistles (except for graphics) turned on.
Integrated Graphics: PowerVR SGX545
A few weeks ago some rumors came up about the integrated graphics core, which is based on Imagination Technologies SGX545 core, having driver problems and that Intel therefore would not be (able to) advertising the Cedar Trails Atom CPUs as the DX10.1-parts that they truly are. According to the data sheet this seems to be true. The feature list of the integrated GPU starts right with
- Support Directx*9 compliant Pixel Shader* v3.0 and OGL 3.0
And just on the next page, near the end of the list, there's a mention of DirectX 10. The GPU seems to support it, but only parts of the features are mentioned such as 64-bit FP color formats or NPO2 (texture?) tiling. There's also an asterisk indicating a remark, but that is curiously missing in the current version of the document. Interestingly, next to the graphics core frequency being stated as 640 MHz (D2700, N2800) or 400 MHz (D2500, N2600), there's also a 200 MHz render clock. Right now, I am not really sure, if that's referring to the pixel-slash-display pipes in contrast to PowerVR SGX's Universal Scalable Shader Engine (USSE) as the graphics core. In the clocking section, there's yet another clock speed given as "The Display core clock Frequency" by SKUs.
Cedar-Trail SKU | Display Core Clock Frequency |
D2700/D2500 | 355 |
N2800 | 267 |
N2600 | 200 |
The 27 MHz crystal required to drive those frequencies can range from 26.9919 to 27.0081 MHz. The integrated PowerVR SGX 545 core has two display pipelines available, allowing to drive two fully independet displays on your device. edit: To be more precise: The core connects to two display outputs provided on-chip, those are not a feature of the licensed SGX core itself.
The feature set of the integrated graphics is described as such. Intel has implemented a two-pipe version of PowerVR SGX545 with a peak fill rate of 4 ppc. The vertex processing or rather the triangle transformation takes 8 clocks. Maximum texture size is given by Intel as 2.048x2.048 – again an indication of not going for DX10 spec. The D2000/N2000 series supports either 2x or 4x rotated grid multi-sampling anti-aliasing at the discretion of application. Of course, as SGX545 is a Tile-Based Deferred Rendering architecture, the choice of anti-aliasing modes will only affect the performance of image synthesis processor and not the shading and texturing part of the pipeline.
There's of coure SGX545's standard set of features describing the FP32 scalar USS-Engine (with available 2-way split for 16 Bit integers and 4-way split for 8 Bit integers) which I'll just copy and paste here for sake of completeness.
Unified programming mode
• Multi-threaded with 16 concurrently running threads and up to 64 data simultaneous instances
• Zero-cost swapping in/out of threads
• Cached program execution model – max program size 262144 instructions
• Dedicated pixel processing instructions
• Dedicated vertex processing instructions
• 4096 32-bit registers and 48 40-bit registers
• 3-way 10 bit integer and 4-way 10 bit integer operations
SIMD pipeline supporting operations in
• 32-Bit IEEE Float
• 2-way, 16-bit fixed point
• 4-way, 8-bit integer
• 32-bit integer
• 32-bit bit-wise (logical only)
Static and Dynamic flow control
• Subroutine calls
• Loops
• Conditional branches
• Zero-cost instruction predication
Procedural Geometry
• Allows generation of more primitives on output compared with input data
• Effective geometry compression
•High order surface support
External data access
• Permits reads from main memory by cache (can be bypassed)
• Permits writes to main memory
• Data fence facility provided
• Multi-threaded with 16 concurrently running threads and up to 64 data simultaneous instances
• Zero-cost swapping in/out of threads
• Cached program execution model – max program size 262144 instructions
• Dedicated pixel processing instructions
• Dedicated vertex processing instructions
• 4096 32-bit registers and 48 40-bit registers
• 3-way 10 bit integer and 4-way 10 bit integer operations
SIMD pipeline supporting operations in
• 32-Bit IEEE Float
• 2-way, 16-bit fixed point
• 4-way, 8-bit integer
• 32-bit integer
• 32-bit bit-wise (logical only)
Static and Dynamic flow control
• Subroutine calls
• Loops
• Conditional branches
• Zero-cost instruction predication
Procedural Geometry
• Allows generation of more primitives on output compared with input data
• Effective geometry compression
•High order surface support
External data access
• Permits reads from main memory by cache (can be bypassed)
• Permits writes to main memory
• Data fence facility provided
Update, Jan. 20th, 2012: I've recently stumbled upon volume two of Intels datasheets, which has made it's way to their servers as well (PDF, 2.91 MiB). Additionally, volume 1 one of the datasheets has been updated to revision 002, which you can grab via the provided link above or the attached file below.
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